In today's rapidly advancing semiconductor manufacturing industry, the integrated circuit chips that form semiconductor devices include a multitude of conductive structures such as interconnect lines, contacts and vias. The performance of a semiconductor device depends upon device speed and there is an aggressive, continuing push to increase device speed and reliability. The speed and reliability of a device are highly dependent upon the resistivity and proper formation of interconnect, which includes contacts, vias, and metal lines. As such, various materials and combinations of materials have been used in an attempt to provide low-resistance interconnect structures with good step coverage and interfacial adhesion properties. As technologies advance, device features become smaller and smaller and the aspect ratios of the openings within which contacts, vias and other conductive structures are formed, becomes higher. This makes it more difficult to completely fill the contact or via openings in a void-free manner necessary to produce a suitably low contact or via resistance, using conventional technology. The reliability of a semiconductor device is also extremely critical and reliability can be degraded or compromised by poor formation of interconnect structures.
It would therefore be desirable to produce conductive interconnect structures such as contacts, vias and conductive lines, with low resistance and high reliability and which are scalable to the reduced geometries and high aspect ratios required in today's semiconductor manufacturing industry. It is within this context the following disclosure arises.